1. Field of the Invention
The present invention relates to a digital-analogue transformer, and in particular, to a resistor string type digital-analogue transformer.
2. Background of the Related Art
A digital-analogue transformer is a device that transforms digital input signals into analogue output signals and is used in many fields such as A/V signal processors, measurement/control systems and the like. There are various types of the digital-analogue transformers such as resistor string, current cell matrix, sigma-delta, etc.
FIG. 1 shows a related art resistor string type digital-analogue transformer. As shown in FIG. 1, a digital-analogue transformer 102 is constituted with a high reference voltage generator 106a, a low reference voltage generator 106b, a resistor string 104, a switch 110, a decoder 112, a buffer 114, and a bias voltage generator 116, which are all built in a block.
The high and low reference voltage generators 106a and 106b respectively generate a high reference voltage VREFH and a low reference voltage VREFI. that are between the analogue power source voltage AVDD and an analogue ground AGND. The low reference voltage VREFL is a little bit higher than the analogue ground AGND. The high reference voltage VREFH is a little bit lower than an analogue power source voltage AVDD. The reference voltage generator 106 produces stable reference voltages VREFH and VREFL despite the fluctuation of analogue power source voltage levels AVDDxcx9cAGND caused by external influences.
The resistor string 104 is constituted with a plurality of series connected resistors that have identical resistances. The high reference voltage VREFH and the low reference voltage VREFL are applied to both ends of the resistor string 104, respectively. The high reference voltage VREFH brings about successive voltage drops at the respective resistors of the resistor string 104 to produce divided voltages VDIV at the respective nodes therein. When the number of resistors constructing the resistor string 104 is n, the number of produced divided voltages VDIS is n and each of the intervals is VREFH/n equivalently. Resolution of the digital-analogue transformer depends on the number of the divided voltages VDIV and the interval. As the resolution is increased, the analogue output is more precisely produced.
The decoder 112 generates a decoded digital signal DEC by decoding a digital input signal D[0:9]. The switch 110 receives the divided voltages VDIV from the resistor string 104 and is controlled by the decoded digital signal DEC outputted from the decoder 112. The switch 110 outputs a divided voltage VDIV as a DC voltage VD having a level that corresponds to the value of the digital input signal D[0:9].
The buffer 114 is a unity gain voltage amplifier that has a non-inversion input terminal+receive a reference voltage VCOM, while an output AOUT is fed back to an inversion input terminalxe2x88x92. The buffer 114 receives the DC voltage VDC at the inversion input terminalxe2x88x92. Then, the buffer 114 outputs the analogue output voltage AOUT by maintaining its voltage level and by improving only its current driving ability. A bias voltage VBIAS is applied to the buffer 114, which is supplied by the built-in bias voltage generator 116.
FIG. 2 shows a block diagram of a related art multi-channel digital-analogue transformer. As shown in FIG. 2, a plurality of unit digital-analogue transforming channels (102a, 102b, . . . , 102m) being m in number are connected in parallel to one another to constitute a multi-channel digital-analogue transformer. Each of the unit digital-analogue transforming channels 102 generates an analogue output voltage AOUT by receiving a digital input signal D[n0:n9] of 10 bits. Further, each of the digital-analogue transforming channels 102 is connected to an analogue power source voltage AVDD and an analogue ground AGND and shares a reference voltage VCOM.
Offset, differential non-linearity (DNL), integral non-linearity (INL), signal to noise (SNR), and the like pertain to the characteristics of the digital-analogue transformer. FIG. 3 shows a graph of the offset error. As shown in FIG. 3, an output voltage corresponding to the lowest bit of a digital input signal is not 0 but 1/n V, which is called an offset error. When the digital-analogue transformer is formed with multi-channels, it is difficult to produce a precise analogue output voltage provided that the respective offsets among the channels differ in size.
As described above, the related art digital-analogue transformers have various problems. The number of resistors of a resistor string should be increased, however, as the number of bits of a digital input signal increases, an increased or a larger chip size is required. Further, constitutions of a high reference voltage generator and a low reference voltage generator should be reconstructed whenever a system is designed to increase or reduce a swing width of an analogue output voltage in accordance with the system characteristics. Also, characteristics of DNL, INL, SNR and the like are deteriorated because of a xe2x80x98glitchxe2x80x99 during a switching mode of the switch. In addition, offset differences between the respective channels of a multi-channel digital-analogue transformer increase, thereby generating errors.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a method of fabricating a semiconductor device that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a digital-analogue transformer that improves or increases resolution by inserting an interpolation voltage between the divided voltages generated from a resistor string.
Another object of the present invention is to provide a digital-analogue transformer that changes a swing width of an output voltage by placing an amplifier using a feedback RC parallel circuit on an output stage.
Another object of the present invention is to provide a digital-analogue transformer that reduces xe2x80x98glitchxe2x80x99 based on a switching operation.
Another object of the present invention is to provide a digital-analogue transformer that reduces a xe2x80x98glitchxe2x80x99 in a circuit caused by a switching operation by connecting a capacitor to a resistor string and a reference voltage input terminal.
Another object of the present invention is to provide a digital-analogue transformer that reduces an offset difference generated from respective channels.
Another object of the present invention is to provide a digital-analogue transformer that reduces an offset difference generated among respective channels by having each of the respective digital-analogue transforming channels share a reference voltage generator and a bias voltage generator.
To achieve at least these and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a digital to analogue converter according to the present invention is provided that includes a voltage divider that generates a plurality of first divided voltages and a plurality of second divided voltages from corresponding nodes of a plurality of serial resistors coupled between a high reference voltage and a low reference voltage, a switch coupled to the voltage divider that receives a digital signal, wherein the switch outputs one of the first divided voltages as a first DC voltage corresponding to upper m bits of the digital signal and outputs one of the second divided voltages as a second DC voltage corresponding to lower n bits of the digital input signal, and a voltage adder that generates an added voltage by adding the first DC voltage to the second DC voltage.
To further achieve the above objects in a whole or in part a digital-analogue transformer according to the present invention is provided that includes a voltage divider that generates a first divided voltage and a second divided voltage from nodes of a plurality of serial resistors coupled between a high reference voltage and a low reference voltage, a decoder that generates a decoded digital signal by decoding a digital input signal a switch coupled to the voltage divider that is controlled by the decoded digital signal, wherein the switch outputs a divided voltage corresponding to the digital input signal, and an output voltage controller that generates an analogue output voltage by receiving the divided voltage through an amplifier having an amplifier output amplitude determined by a feedback RC parallel circuit.
To further achieve the above objects in a whole or in part a digital-analogue transformer according to the present invention is provided that includes a voltage divider that generates a first divided voltage and a second divided voltage from nodes of a plurality of resistors coupled in series as a resistor string between a high reference voltage and a low reference voltage, a decoder that generates a decoded digital signal by decoding a digital input signal, a switch coupled to the voltage divider that is controlled by the decoded digital signal, wherein the switch outputs the first divided voltage as a first DC voltage corresponding to upper m bits of the digital input signal, and wherein the switch outputs the second divided voltage as a second DC voltage corresponding to lower n bits of the digital input signal, a voltage adder that generates an added voltage by adding the first DC voltage to the second DC voltage, and an output voltage controller generating an analogue output voltage by receiving the added voltage through an amplifier having an upper output amplitude determined by a feedback RC parallel circuit.
To further achieve the above objects in a whole or in part a digital-analogue transformer according to the present invention is provided that includes a reference voltage generator that generates a high reference voltage lower than a first analogue reference voltage, wherein the reference voltage generator generates a low reference voltage higher than a second analogue reference voltage, wherein the high reference voltage is greater than the low reference voltage, a bias voltage generator that generates a bias voltage, and a plurality of unit digital-analogue transforming channels each including a voltage divider that generates a first divided voltage and a second divided voltage from nodes of a plurality of resistors connected between the high reference voltage and the low reference voltage, a decoder that generates a decoded digital signal by decoding an input signal, a switch controlled by the decoded digital signal, wherein the switch outputs the first divided voltage as a first DC voltage corresponding to upper m bits of the decoded digital signal, wherein the switch outputs the second divided voltage as a second DC voltage corresponding to lower n bits of the decoded digital input signal, a voltage adder that generates an added voltage by adding the first DC voltage to the second DC voltage, and an output voltage controller that generates an analogue output voltage by receiving the added voltage at an input terminal of an amplifier having an upper output amplitude determined by a feedback RC parallel circuit, and wherein the plurality of the unit digital-analogue transforming channels share the reference voltage generator and the bias voltage generator.
To further achieve the above objects in a whole or in part a digital-analogue transforming means according to the present invention is provided that includes voltage distributing means for generating a plurality of first divided voltages and a plurality of second divided voltages from nodes of a plurality of resistor means coupled in series between a high reference voltage and a low reference voltage, decoding means for generating a decoded digital signal by decoding a digital input signal, switching means controlled by the decoded digital signal for switching one of the first divided voltages as a first DC voltage corresponding to upper m bits of the digital input signal, wherein the switching means switches one of the second divided voltages as a second DC voltage corresponding to lower n bits of the decoded digital input signal, voltage adding means for generating an added voltage by adding the first DC voltage to the second DC voltage, and output voltage controlling means for generating an analogue output voltage by receiving the added voltage through an amplifier means having an upper output amplitude determined by a feedback RC parallel circuit means.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.